There are integrated BiCMOS semiconductor circuits that have active moat areas in silicon. These moat areas include electrically active components of the semiconductor circuit, the active components comprising active window structures for base and/or emitter windows. The semiconductor circuit has zones where silicon is left to form dummy moat areas which do not include electrically active components. The semiconductor circuit further has isolation trenches to separate the active moat areas from each other and from the dummy moat areas.
In the production of integrated BiCMOS semiconductor circuits, a plurality of silicon and oxide layers are deposited on a support wafer and patterned in consecutive steps. An example of such a stack of layers is shown in a schematic sectional view in FIG. 1 of the appending drawings. Upon patterning, stacks of layers, generally referred to as 1 in FIG. 1, form so called active moat areas 2. These areas are islands which will in the end contain electrically active components of the semiconductor circuit. The active moat areas 2 are separated by trenches 3 formed into the layers by etching. The trenches are filled with an isolating material 4 such as oxide. Above a trench 3, a shallow depression 3a may form in the oxide layer 4. Depending on the layout of the circuit, the distance between two adjacent active moat areas 2 can be wide, resulting in a broad trench 5. Where the trenches are too wide, deep depressions 6 in the oxide layer 4 will occur.
These deep depressions 6 become a problem when performing a process of chemical mechanical polishing (CMP) on a layer.
To avoid the occurrence of depressions in the oxide layer 4, so called dummy moat areas 7 are left (FIG. 2). These areas 7 are islands which are designed not to include electrically active components but simply to avoid large and deep depressions. Incidentally, the technique of leaving dummy moat areas 7 is known in the prior art to ensure correct planarization.
Anisotropic plasma etching is used for the etching of fine structures. The etching duration may be pre-determined, but if the underlying layer is thin, e.g., a thin oxide film, it is essential to stop the etching in time before the underlying silicon gets damaged, but not before the desired structure is completed. This is particularly essential when dealing with small structures. Due to inaccuracies in the thickness of the layer to be etched and in the etchant composition, the calculation of the etching duration cannot be exact. Still, the completion of the etching process can be controlled more accurately by detecting an endpoint in the process. As explained in the article entitled, “Tungsten silicide and tungsten polycide anisotropic dry etch process for highly controlled dimensions and profiles,” by R. Bashir, et al., in J. Vac. Sci. Technol., Vol. 16(4), July/August 1998, pages 2118-2120, and in U.S. Pat. No. 6,444,542B2, the endpoint of the etching process can be detected by a change in the composition of the optical radiation by optical emission spectroscopy, by the plasma characteristics, i.e., high-frequency harmonics, or the discharge current, or by a change in reflection properties of the wafer when the etching process reaches the underlying layer. Reaching an oxide layer can also be used as an endpoint check (U.S. Pat. No. 5,496,764A). But, if the surface to be etched is very small compared to the total wafer surface, detection of the endpoint of the etching process with this approach is no longer possible.
In U. S. Pat. No. 6,004,829A, it is proposed to enlarge the surface to be etched by inserting additional pad areas in forming an EPROM device. It is, however, well-known that large areas exhibit a higher etch-rate than small structures. If now the window structures to be etched are very small and delicate, and dummy surfaces are used for etch endpoint detection, the etch endpoint signal will occur prematurely, so that the optimum moment in time when the etching process should be terminated cannot be determined with sufficient precision.